URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] - Rev 35

Rev	Log message	Author	Age	Path
35	Updated the New Documents - ver 0.1	dinesha	4477d 17h	/sdr_ctrl/trunk
34	Removed the older version	dinesha	4477d 17h	/sdr_ctrl/trunk
33	clean up	dinesha	4477d 18h	/sdr_ctrl/trunk
32	Debug is enable through +define	dinesha	4479d 17h	/sdr_ctrl/trunk
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4479d 17h	/sdr_ctrl/trunk
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4479d 17h	/sdr_ctrl/trunk
29	SDRAM top and core related run file list are added into svn	dinesha	4479d 17h	/sdr_ctrl/trunk
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	4479d 17h	/sdr_ctrl/trunk
27	Golden log file corresponds the SDRAM core level test case are added into svn	dinesha	4480d 15h	/sdr_ctrl/trunk
26	invalid log files are removed	dinesha	4480d 15h	/sdr_ctrl/trunk
25	tb.sv is renamed as tb_top	dinesha	4480d 16h	/sdr_ctrl/trunk
24	Clean Up	dinesha	4480d 16h	/sdr_ctrl/trunk
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4481d 21h	/sdr_ctrl/trunk
22	Pad sdram clock added	dinesha	4481d 21h	/sdr_ctrl/trunk
21	Clean up	dinesha	4481d 21h	/sdr_ctrl/trunk
20	8 Bit SDARM support is added	dinesha	4483d 16h	/sdr_ctrl/trunk
19	8 Bit SDRAM Support added	dinesha	4483d 16h	/sdr_ctrl/trunk
18	8 Bit SDRAM Support is added	dinesha	4483d 16h	/sdr_ctrl/trunk
17	micron 8 bit memory models are added into svn	dinesha	4483d 16h	/sdr_ctrl/trunk
16	8 Bit SDRAM Support is added	dinesha	4483d 16h	/sdr_ctrl/trunk