OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] - Rev 38

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
38 Port Name clean up dinesha 4495d 01h /sdr_ctrl/trunk/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4495d 02h /sdr_ctrl/trunk/
36 Clean up dinesha 4495d 17h /sdr_ctrl/trunk/
35 Updated the New Documents - ver 0.1 dinesha 4495d 19h /sdr_ctrl/trunk/
34 Removed the older version dinesha 4495d 19h /sdr_ctrl/trunk/
33 clean up dinesha 4495d 19h /sdr_ctrl/trunk/
32 Debug is enable through +define dinesha 4497d 18h /sdr_ctrl/trunk/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4497d 18h /sdr_ctrl/trunk/
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4497d 19h /sdr_ctrl/trunk/
29 SDRAM top and core related run file list are added into svn dinesha 4497d 19h /sdr_ctrl/trunk/
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4497d 19h /sdr_ctrl/trunk/
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4498d 17h /sdr_ctrl/trunk/
26 invalid log files are removed dinesha 4498d 17h /sdr_ctrl/trunk/
25 tb.sv is renamed as tb_top dinesha 4498d 17h /sdr_ctrl/trunk/
24 Clean Up dinesha 4498d 17h /sdr_ctrl/trunk/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4499d 22h /sdr_ctrl/trunk/
22 Pad sdram clock added dinesha 4499d 22h /sdr_ctrl/trunk/
21 Clean up dinesha 4499d 22h /sdr_ctrl/trunk/
20 8 Bit SDARM support is added dinesha 4501d 17h /sdr_ctrl/trunk/
19 8 Bit SDRAM Support added dinesha 4501d 17h /sdr_ctrl/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.