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[/] [sdr_ctrl/] [trunk/] - Rev 40

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Rev Log message Author Age Path
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4522d 08h /sdr_ctrl/trunk/
39 Test Bench upgradation with bigger data burst size dinesha 4522d 09h /sdr_ctrl/trunk/
38 Port Name clean up dinesha 4523d 14h /sdr_ctrl/trunk/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4523d 15h /sdr_ctrl/trunk/
36 Clean up dinesha 4524d 06h /sdr_ctrl/trunk/
35 Updated the New Documents - ver 0.1 dinesha 4524d 08h /sdr_ctrl/trunk/
34 Removed the older version dinesha 4524d 08h /sdr_ctrl/trunk/
33 clean up dinesha 4524d 08h /sdr_ctrl/trunk/
32 Debug is enable through +define dinesha 4526d 07h /sdr_ctrl/trunk/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4526d 07h /sdr_ctrl/trunk/
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4526d 07h /sdr_ctrl/trunk/
29 SDRAM top and core related run file list are added into svn dinesha 4526d 07h /sdr_ctrl/trunk/
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4526d 08h /sdr_ctrl/trunk/
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4527d 06h /sdr_ctrl/trunk/
26 invalid log files are removed dinesha 4527d 06h /sdr_ctrl/trunk/
25 tb.sv is renamed as tb_top dinesha 4527d 06h /sdr_ctrl/trunk/
24 Clean Up dinesha 4527d 06h /sdr_ctrl/trunk/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4528d 11h /sdr_ctrl/trunk/
22 Pad sdram clock added dinesha 4528d 11h /sdr_ctrl/trunk/
21 Clean up dinesha 4528d 11h /sdr_ctrl/trunk/

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