OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] - Rev 40

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4477d 23h /sdr_ctrl/trunk/
39 Test Bench upgradation with bigger data burst size dinesha 4477d 23h /sdr_ctrl/trunk/
38 Port Name clean up dinesha 4479d 04h /sdr_ctrl/trunk/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4479d 06h /sdr_ctrl/trunk/
36 Clean up dinesha 4479d 21h /sdr_ctrl/trunk/
35 Updated the New Documents - ver 0.1 dinesha 4479d 22h /sdr_ctrl/trunk/
34 Removed the older version dinesha 4479d 22h /sdr_ctrl/trunk/
33 clean up dinesha 4479d 23h /sdr_ctrl/trunk/
32 Debug is enable through +define dinesha 4481d 22h /sdr_ctrl/trunk/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4481d 22h /sdr_ctrl/trunk/
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4481d 22h /sdr_ctrl/trunk/
29 SDRAM top and core related run file list are added into svn dinesha 4481d 22h /sdr_ctrl/trunk/
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4481d 22h /sdr_ctrl/trunk/
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4482d 20h /sdr_ctrl/trunk/
26 invalid log files are removed dinesha 4482d 20h /sdr_ctrl/trunk/
25 tb.sv is renamed as tb_top dinesha 4482d 20h /sdr_ctrl/trunk/
24 Clean Up dinesha 4482d 20h /sdr_ctrl/trunk/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4484d 02h /sdr_ctrl/trunk/
22 Pad sdram clock added dinesha 4484d 02h /sdr_ctrl/trunk/
21 Clean up dinesha 4484d 02h /sdr_ctrl/trunk/
20 8 Bit SDARM support is added dinesha 4485d 20h /sdr_ctrl/trunk/
19 8 Bit SDRAM Support added dinesha 4485d 20h /sdr_ctrl/trunk/
18 8 Bit SDRAM Support is added dinesha 4485d 20h /sdr_ctrl/trunk/
17 micron 8 bit memory models are added into svn dinesha 4485d 21h /sdr_ctrl/trunk/
16 8 Bit SDRAM Support is added dinesha 4485d 21h /sdr_ctrl/trunk/
15 Port cleanup dinesha 4488d 21h /sdr_ctrl/trunk/
14 Unnecessary device config are removed dinesha 4488d 21h /sdr_ctrl/trunk/
13 column bit are made progrmmable dinesha 4488d 22h /sdr_ctrl/trunk/
12 Column Bits are made programmable dinesha 4488d 22h /sdr_ctrl/trunk/
11 SDRAM Specification document added into SVN dinesha 4491d 23h /sdr_ctrl/trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.