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[/] [sdr_ctrl/] [trunk/] - Rev 45

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Rev Log message Author Age Path
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 5054d 19h /sdr_ctrl/trunk/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 5056d 17h /sdr_ctrl/trunk/
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 5056d 19h /sdr_ctrl/trunk/
42 Bug fix in read access is fixed dinesha 5056d 19h /sdr_ctrl/trunk/
41 Updated Spec ver 0.1 is added back to svn dinesha 5056d 20h /sdr_ctrl/trunk/
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 5057d 13h /sdr_ctrl/trunk/
39 Test Bench upgradation with bigger data burst size dinesha 5057d 13h /sdr_ctrl/trunk/
38 Port Name clean up dinesha 5058d 18h /sdr_ctrl/trunk/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 5058d 20h /sdr_ctrl/trunk/
36 Clean up dinesha 5059d 11h /sdr_ctrl/trunk/
35 Updated the New Documents - ver 0.1 dinesha 5059d 13h /sdr_ctrl/trunk/
34 Removed the older version dinesha 5059d 13h /sdr_ctrl/trunk/
33 clean up dinesha 5059d 13h /sdr_ctrl/trunk/
32 Debug is enable through +define dinesha 5061d 12h /sdr_ctrl/trunk/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 5061d 12h /sdr_ctrl/trunk/
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 5061d 12h /sdr_ctrl/trunk/
29 SDRAM top and core related run file list are added into svn dinesha 5061d 12h /sdr_ctrl/trunk/
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 5061d 12h /sdr_ctrl/trunk/
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 5062d 10h /sdr_ctrl/trunk/
26 invalid log files are removed dinesha 5062d 10h /sdr_ctrl/trunk/
25 tb.sv is renamed as tb_top dinesha 5062d 11h /sdr_ctrl/trunk/
24 Clean Up dinesha 5062d 11h /sdr_ctrl/trunk/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 5063d 16h /sdr_ctrl/trunk/
22 Pad sdram clock added dinesha 5063d 16h /sdr_ctrl/trunk/
21 Clean up dinesha 5063d 16h /sdr_ctrl/trunk/
20 8 Bit SDARM support is added dinesha 5065d 11h /sdr_ctrl/trunk/
19 8 Bit SDRAM Support added dinesha 5065d 11h /sdr_ctrl/trunk/
18 8 Bit SDRAM Support is added dinesha 5065d 11h /sdr_ctrl/trunk/
17 micron 8 bit memory models are added into svn dinesha 5065d 11h /sdr_ctrl/trunk/
16 8 Bit SDRAM Support is added dinesha 5065d 11h /sdr_ctrl/trunk/

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