URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] - Rev 52

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
52	Documentation update for request control and transfer control block	dinesha	4464d 19h	/sdr_ctrl/trunk/
51	FPGA relating timing optimisation done	dinesha	4464d 20h	/sdr_ctrl/trunk/
50	Bug fix the request length is fixe	dinesha	4466d 23h	/sdr_ctrl/trunk/
49	clean up	dinesha	4467d 22h	/sdr_ctrl/trunk/
48	top-level cleanup	dinesha	4467d 23h	/sdr_ctrl/trunk/
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4467d 23h	/sdr_ctrl/trunk/
46	test bench upgrade + rtl cleanup	dinesha	4469d 23h	/sdr_ctrl/trunk/
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4470d 04h	/sdr_ctrl/trunk/
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4472d 02h	/sdr_ctrl/trunk/
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4472d 03h	/sdr_ctrl/trunk/
42	Bug fix in read access is fixed	dinesha	4472d 04h	/sdr_ctrl/trunk/
41	Updated Spec ver 0.1 is added back to svn	dinesha	4472d 05h	/sdr_ctrl/trunk/
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4472d 22h	/sdr_ctrl/trunk/
39	Test Bench upgradation with bigger data burst size	dinesha	4472d 22h	/sdr_ctrl/trunk/
38	Port Name clean up	dinesha	4474d 03h	/sdr_ctrl/trunk/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4474d 05h	/sdr_ctrl/trunk/
36	Clean up	dinesha	4474d 20h	/sdr_ctrl/trunk/
35	Updated the New Documents - ver 0.1	dinesha	4474d 21h	/sdr_ctrl/trunk/
34	Removed the older version	dinesha	4474d 22h	/sdr_ctrl/trunk/
33	clean up	dinesha	4474d 22h	/sdr_ctrl/trunk/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] - Rev 52

Filtering Options