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[/] [sdr_ctrl/] [trunk/] - Rev 58

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Rev Log message Author Age Path
58 Read Data is register on RD_FAST=0 case dinesha 4627d 20h /sdr_ctrl/trunk/
57 Synthesis constraints are added dinesha 4628d 11h /sdr_ctrl/trunk/
56 FPGA Synth optimisation dinesha 4628d 12h /sdr_ctrl/trunk/
55 FPGA Synthesis timing optimisation dinesha 4628d 12h /sdr_ctrl/trunk/
54 FPGA Timing Optimisation dinesha 4631d 10h /sdr_ctrl/trunk/
53 Test bench upgradation dinesha 4632d 10h /sdr_ctrl/trunk/
52 Documentation update for request control and transfer control block dinesha 4632d 10h /sdr_ctrl/trunk/
51 FPGA relating timing optimisation done dinesha 4632d 11h /sdr_ctrl/trunk/
50 Bug fix the request length is fixe dinesha 4634d 14h /sdr_ctrl/trunk/
49 clean up dinesha 4635d 13h /sdr_ctrl/trunk/
48 top-level cleanup dinesha 4635d 13h /sdr_ctrl/trunk/
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4635d 13h /sdr_ctrl/trunk/
46 test bench upgrade + rtl cleanup dinesha 4637d 14h /sdr_ctrl/trunk/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4637d 18h /sdr_ctrl/trunk/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4639d 17h /sdr_ctrl/trunk/
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4639d 18h /sdr_ctrl/trunk/
42 Bug fix in read access is fixed dinesha 4639d 18h /sdr_ctrl/trunk/
41 Updated Spec ver 0.1 is added back to svn dinesha 4639d 20h /sdr_ctrl/trunk/
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4640d 13h /sdr_ctrl/trunk/
39 Test Bench upgradation with bigger data burst size dinesha 4640d 13h /sdr_ctrl/trunk/

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