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[/] [sdr_ctrl/] [trunk/] - Rev 65

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Rev Log message Author Age Path
65 Updated Log file with CAS latency support 4,5 dinesha 4352d 02h /sdr_ctrl/trunk/
64 CAS Latency support added for 4,5 dinesha 4352d 02h /sdr_ctrl/trunk/
63 FPGA Bench mark results are added dinesha 4471d 01h /sdr_ctrl/trunk/
62 Synthesis constraint for simplify dinesha 4471d 01h /sdr_ctrl/trunk/
61 RTL file list are added into SVN dinesha 4471d 02h /sdr_ctrl/trunk/
60 warning cleanup dinesha 4471d 02h /sdr_ctrl/trunk/
59 Control path request and data are register now for better FPGA timing dinesha 4471d 02h /sdr_ctrl/trunk/
58 Read Data is register on RD_FAST=0 case dinesha 4471d 02h /sdr_ctrl/trunk/
57 Synthesis constraints are added dinesha 4471d 16h /sdr_ctrl/trunk/
56 FPGA Synth optimisation dinesha 4471d 18h /sdr_ctrl/trunk/
55 FPGA Synthesis timing optimisation dinesha 4471d 18h /sdr_ctrl/trunk/
54 FPGA Timing Optimisation dinesha 4474d 15h /sdr_ctrl/trunk/
53 Test bench upgradation dinesha 4475d 16h /sdr_ctrl/trunk/
52 Documentation update for request control and transfer control block dinesha 4475d 16h /sdr_ctrl/trunk/
51 FPGA relating timing optimisation done dinesha 4475d 16h /sdr_ctrl/trunk/
50 Bug fix the request length is fixe dinesha 4477d 20h /sdr_ctrl/trunk/
49 clean up dinesha 4478d 19h /sdr_ctrl/trunk/
48 top-level cleanup dinesha 4478d 19h /sdr_ctrl/trunk/
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4478d 19h /sdr_ctrl/trunk/
46 test bench upgrade + rtl cleanup dinesha 4480d 20h /sdr_ctrl/trunk/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4481d 00h /sdr_ctrl/trunk/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4482d 22h /sdr_ctrl/trunk/
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4483d 00h /sdr_ctrl/trunk/
42 Bug fix in read access is fixed dinesha 4483d 00h /sdr_ctrl/trunk/
41 Updated Spec ver 0.1 is added back to svn dinesha 4483d 02h /sdr_ctrl/trunk/
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4483d 19h /sdr_ctrl/trunk/
39 Test Bench upgradation with bigger data burst size dinesha 4483d 19h /sdr_ctrl/trunk/
38 Port Name clean up dinesha 4485d 00h /sdr_ctrl/trunk/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4485d 02h /sdr_ctrl/trunk/
36 Clean up dinesha 4485d 16h /sdr_ctrl/trunk/

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