URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] - Rev 65

Rev	Log message	Author	Age	Path
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	5054d 19h	/sdr_ctrl/trunk/
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	5056d 17h	/sdr_ctrl/trunk/
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	5056d 19h	/sdr_ctrl/trunk/
42	Bug fix in read access is fixed	dinesha	5056d 19h	/sdr_ctrl/trunk/
41	Updated Spec ver 0.1 is added back to svn	dinesha	5056d 20h	/sdr_ctrl/trunk/
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	5057d 13h	/sdr_ctrl/trunk/
39	Test Bench upgradation with bigger data burst size	dinesha	5057d 13h	/sdr_ctrl/trunk/
38	Port Name clean up	dinesha	5058d 18h	/sdr_ctrl/trunk/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	5058d 20h	/sdr_ctrl/trunk/
36	Clean up	dinesha	5059d 11h	/sdr_ctrl/trunk/