URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] - Rev 31

Rev	Log message	Author	Age	Path
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4861d 21h	/sdr_ctrl/trunk/rtl/
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4864d 01h	/sdr_ctrl/trunk/rtl/
16	8 Bit SDRAM Support is added	dinesha	4865d 20h	/sdr_ctrl/trunk/rtl/
15	Port cleanup	dinesha	4868d 21h	/sdr_ctrl/trunk/rtl/
13	column bit are made progrmmable	dinesha	4868d 21h	/sdr_ctrl/trunk/rtl/
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4872d 22h	/sdr_ctrl/trunk/rtl/
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4873d 19h	/sdr_ctrl/trunk/rtl/
3	SDRAM controller core files are checked in	dinesha	4880d 06h	/sdr_ctrl/trunk/rtl/
2		dinesha	4882d 22h	/sdr_ctrl/trunk/rtl/