OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] - Rev 35

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
33 clean up dinesha 4517d 05h /sdr_ctrl/trunk/rtl/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4519d 04h /sdr_ctrl/trunk/rtl/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4521d 08h /sdr_ctrl/trunk/rtl/
16 8 Bit SDRAM Support is added dinesha 4523d 03h /sdr_ctrl/trunk/rtl/
15 Port cleanup dinesha 4526d 04h /sdr_ctrl/trunk/rtl/
13 column bit are made progrmmable dinesha 4526d 04h /sdr_ctrl/trunk/rtl/
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4530d 05h /sdr_ctrl/trunk/rtl/
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4531d 02h /sdr_ctrl/trunk/rtl/
3 SDRAM controller core files are checked in dinesha 4537d 12h /sdr_ctrl/trunk/rtl/
2 dinesha 4540d 04h /sdr_ctrl/trunk/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.