OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] - Rev 40

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4522d 22h /sdr_ctrl/trunk/rtl/
38 Port Name clean up dinesha 4524d 03h /sdr_ctrl/trunk/rtl/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4524d 05h /sdr_ctrl/trunk/rtl/
36 Clean up dinesha 4524d 19h /sdr_ctrl/trunk/rtl/
33 clean up dinesha 4524d 22h /sdr_ctrl/trunk/rtl/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4526d 21h /sdr_ctrl/trunk/rtl/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4529d 00h /sdr_ctrl/trunk/rtl/
16 8 Bit SDRAM Support is added dinesha 4530d 20h /sdr_ctrl/trunk/rtl/
15 Port cleanup dinesha 4533d 20h /sdr_ctrl/trunk/rtl/
13 column bit are made progrmmable dinesha 4533d 21h /sdr_ctrl/trunk/rtl/
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4537d 21h /sdr_ctrl/trunk/rtl/
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4538d 19h /sdr_ctrl/trunk/rtl/
3 SDRAM controller core files are checked in dinesha 4545d 05h /sdr_ctrl/trunk/rtl/
2 dinesha 4547d 21h /sdr_ctrl/trunk/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.