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[/] [sdr_ctrl/] [trunk/] [rtl/] - Rev 53


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Rev Log message Author Age Path
51 FPGA relating timing optimisation done dinesha 4545d 13h /sdr_ctrl/trunk/rtl/
50 Bug fix the request length is fixe dinesha 4547d 17h /sdr_ctrl/trunk/rtl/
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4548d 16h /sdr_ctrl/trunk/rtl/
46 test bench upgrade + rtl cleanup dinesha 4550d 17h /sdr_ctrl/trunk/rtl/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4550d 21h /sdr_ctrl/trunk/rtl/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4552d 19h /sdr_ctrl/trunk/rtl/
42 Bug fix in read access is fixed dinesha 4552d 21h /sdr_ctrl/trunk/rtl/
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4553d 16h /sdr_ctrl/trunk/rtl/
38 Port Name clean up dinesha 4554d 21h /sdr_ctrl/trunk/rtl/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4554d 23h /sdr_ctrl/trunk/rtl/
36 Clean up dinesha 4555d 13h /sdr_ctrl/trunk/rtl/
33 clean up dinesha 4555d 16h /sdr_ctrl/trunk/rtl/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4557d 15h /sdr_ctrl/trunk/rtl/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4559d 18h /sdr_ctrl/trunk/rtl/
16 8 Bit SDRAM Support is added dinesha 4561d 13h /sdr_ctrl/trunk/rtl/
15 Port cleanup dinesha 4564d 14h /sdr_ctrl/trunk/rtl/
13 column bit are made progrmmable dinesha 4564d 15h /sdr_ctrl/trunk/rtl/
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4568d 15h /sdr_ctrl/trunk/rtl/
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4569d 13h /sdr_ctrl/trunk/rtl/
3 SDRAM controller core files are checked in dinesha 4575d 23h /sdr_ctrl/trunk/rtl/

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