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URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

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[/] [sdr_ctrl/] [trunk/] [rtl/] - Rev 55

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Rev Log message Author Age Path
55 FPGA Synthesis timing optimisation dinesha 4456d 17h /sdr_ctrl/trunk/rtl/
54 FPGA Timing Optimisation dinesha 4459d 15h /sdr_ctrl/trunk/rtl/
51 FPGA relating timing optimisation done dinesha 4460d 16h /sdr_ctrl/trunk/rtl/
50 Bug fix the request length is fixe dinesha 4462d 20h /sdr_ctrl/trunk/rtl/
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4463d 19h /sdr_ctrl/trunk/rtl/
46 test bench upgrade + rtl cleanup dinesha 4465d 19h /sdr_ctrl/trunk/rtl/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4466d 00h /sdr_ctrl/trunk/rtl/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4467d 22h /sdr_ctrl/trunk/rtl/
42 Bug fix in read access is fixed dinesha 4468d 00h /sdr_ctrl/trunk/rtl/
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4468d 18h /sdr_ctrl/trunk/rtl/
38 Port Name clean up dinesha 4469d 23h /sdr_ctrl/trunk/rtl/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4470d 01h /sdr_ctrl/trunk/rtl/
36 Clean up dinesha 4470d 16h /sdr_ctrl/trunk/rtl/
33 clean up dinesha 4470d 18h /sdr_ctrl/trunk/rtl/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4472d 17h /sdr_ctrl/trunk/rtl/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4474d 21h /sdr_ctrl/trunk/rtl/
16 8 Bit SDRAM Support is added dinesha 4476d 16h /sdr_ctrl/trunk/rtl/
15 Port cleanup dinesha 4479d 17h /sdr_ctrl/trunk/rtl/
13 column bit are made progrmmable dinesha 4479d 17h /sdr_ctrl/trunk/rtl/
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4483d 18h /sdr_ctrl/trunk/rtl/

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