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[/] [sdr_ctrl/] [trunk/] [rtl/] - Rev 69

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Rev Log message Author Age Path
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4025d 15h /sdr_ctrl/trunk/rtl/
67 time scale removed dinesha 4095d 13h /sdr_ctrl/trunk/rtl/
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4343d 14h /sdr_ctrl/trunk/rtl/
64 CAS Latency support added for 4,5 dinesha 4343d 22h /sdr_ctrl/trunk/rtl/
61 RTL file list are added into SVN dinesha 4462d 22h /sdr_ctrl/trunk/rtl/
60 warning cleanup dinesha 4462d 22h /sdr_ctrl/trunk/rtl/
59 Control path request and data are register now for better FPGA timing dinesha 4462d 22h /sdr_ctrl/trunk/rtl/
58 Read Data is register on RD_FAST=0 case dinesha 4462d 22h /sdr_ctrl/trunk/rtl/
55 FPGA Synthesis timing optimisation dinesha 4463d 13h /sdr_ctrl/trunk/rtl/
54 FPGA Timing Optimisation dinesha 4466d 11h /sdr_ctrl/trunk/rtl/
51 FPGA relating timing optimisation done dinesha 4467d 12h /sdr_ctrl/trunk/rtl/
50 Bug fix the request length is fixe dinesha 4469d 16h /sdr_ctrl/trunk/rtl/
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4470d 15h /sdr_ctrl/trunk/rtl/
46 test bench upgrade + rtl cleanup dinesha 4472d 16h /sdr_ctrl/trunk/rtl/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4472d 20h /sdr_ctrl/trunk/rtl/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4474d 18h /sdr_ctrl/trunk/rtl/
42 Bug fix in read access is fixed dinesha 4474d 20h /sdr_ctrl/trunk/rtl/
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4475d 14h /sdr_ctrl/trunk/rtl/
38 Port Name clean up dinesha 4476d 19h /sdr_ctrl/trunk/rtl/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4476d 21h /sdr_ctrl/trunk/rtl/

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