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[/] [sdr_ctrl/] [trunk/] [rtl/] - Rev 70

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Rev Log message Author Age Path
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4065d 04h /sdr_ctrl/trunk/rtl/
67 time scale removed dinesha 4135d 02h /sdr_ctrl/trunk/rtl/
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4383d 03h /sdr_ctrl/trunk/rtl/
64 CAS Latency support added for 4,5 dinesha 4383d 11h /sdr_ctrl/trunk/rtl/
61 RTL file list are added into SVN dinesha 4502d 10h /sdr_ctrl/trunk/rtl/
60 warning cleanup dinesha 4502d 10h /sdr_ctrl/trunk/rtl/
59 Control path request and data are register now for better FPGA timing dinesha 4502d 11h /sdr_ctrl/trunk/rtl/
58 Read Data is register on RD_FAST=0 case dinesha 4502d 11h /sdr_ctrl/trunk/rtl/
55 FPGA Synthesis timing optimisation dinesha 4503d 02h /sdr_ctrl/trunk/rtl/
54 FPGA Timing Optimisation dinesha 4506d 00h /sdr_ctrl/trunk/rtl/
51 FPGA relating timing optimisation done dinesha 4507d 01h /sdr_ctrl/trunk/rtl/
50 Bug fix the request length is fixe dinesha 4509d 05h /sdr_ctrl/trunk/rtl/
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4510d 04h /sdr_ctrl/trunk/rtl/
46 test bench upgrade + rtl cleanup dinesha 4512d 04h /sdr_ctrl/trunk/rtl/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4512d 09h /sdr_ctrl/trunk/rtl/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4514d 07h /sdr_ctrl/trunk/rtl/
42 Bug fix in read access is fixed dinesha 4514d 09h /sdr_ctrl/trunk/rtl/
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4515d 03h /sdr_ctrl/trunk/rtl/
38 Port Name clean up dinesha 4516d 08h /sdr_ctrl/trunk/rtl/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4516d 10h /sdr_ctrl/trunk/rtl/

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