OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] - Rev 73

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 973d 15h /sdr_ctrl/trunk/rtl/
71 Warning cleanup dinesha 4018d 16h /sdr_ctrl/trunk/rtl/
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4018d 17h /sdr_ctrl/trunk/rtl/
67 time scale removed dinesha 4088d 16h /sdr_ctrl/trunk/rtl/
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4336d 16h /sdr_ctrl/trunk/rtl/
64 CAS Latency support added for 4,5 dinesha 4337d 00h /sdr_ctrl/trunk/rtl/
61 RTL file list are added into SVN dinesha 4456d 00h /sdr_ctrl/trunk/rtl/
60 warning cleanup dinesha 4456d 00h /sdr_ctrl/trunk/rtl/
59 Control path request and data are register now for better FPGA timing dinesha 4456d 00h /sdr_ctrl/trunk/rtl/
58 Read Data is register on RD_FAST=0 case dinesha 4456d 00h /sdr_ctrl/trunk/rtl/
55 FPGA Synthesis timing optimisation dinesha 4456d 16h /sdr_ctrl/trunk/rtl/
54 FPGA Timing Optimisation dinesha 4459d 14h /sdr_ctrl/trunk/rtl/
51 FPGA relating timing optimisation done dinesha 4460d 14h /sdr_ctrl/trunk/rtl/
50 Bug fix the request length is fixe dinesha 4462d 18h /sdr_ctrl/trunk/rtl/
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4463d 17h /sdr_ctrl/trunk/rtl/
46 test bench upgrade + rtl cleanup dinesha 4465d 18h /sdr_ctrl/trunk/rtl/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4465d 22h /sdr_ctrl/trunk/rtl/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4467d 20h /sdr_ctrl/trunk/rtl/
42 Bug fix in read access is fixed dinesha 4467d 22h /sdr_ctrl/trunk/rtl/
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4468d 17h /sdr_ctrl/trunk/rtl/
38 Port Name clean up dinesha 4469d 22h /sdr_ctrl/trunk/rtl/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4470d 00h /sdr_ctrl/trunk/rtl/
36 Clean up dinesha 4470d 15h /sdr_ctrl/trunk/rtl/
33 clean up dinesha 4470d 17h /sdr_ctrl/trunk/rtl/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4472d 16h /sdr_ctrl/trunk/rtl/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4474d 20h /sdr_ctrl/trunk/rtl/
16 8 Bit SDRAM Support is added dinesha 4476d 15h /sdr_ctrl/trunk/rtl/
15 Port cleanup dinesha 4479d 15h /sdr_ctrl/trunk/rtl/
13 column bit are made progrmmable dinesha 4479d 16h /sdr_ctrl/trunk/rtl/
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4483d 16h /sdr_ctrl/trunk/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.