OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] - Rev 16

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
16 8 Bit SDRAM Support is added dinesha 4499d 00h /sdr_ctrl/trunk/rtl/core/
15 Port cleanup dinesha 4502d 01h /sdr_ctrl/trunk/rtl/core/
13 column bit are made progrmmable dinesha 4502d 01h /sdr_ctrl/trunk/rtl/core/
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4506d 02h /sdr_ctrl/trunk/rtl/core/
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4506d 23h /sdr_ctrl/trunk/rtl/core/
3 SDRAM controller core files are checked in dinesha 4513d 09h /sdr_ctrl/trunk/rtl/core/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.