URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] - Rev 31

Rev	Log message	Author	Age	Path
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	5036d 09h	/sdr_ctrl/trunk/rtl/core/
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	5038d 13h	/sdr_ctrl/trunk/rtl/core/
16	8 Bit SDRAM Support is added	dinesha	5040d 08h	/sdr_ctrl/trunk/rtl/core/
15	Port cleanup	dinesha	5043d 09h	/sdr_ctrl/trunk/rtl/core/
13	column bit are made progrmmable	dinesha	5043d 09h	/sdr_ctrl/trunk/rtl/core/
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	5047d 10h	/sdr_ctrl/trunk/rtl/core/
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	5048d 07h	/sdr_ctrl/trunk/rtl/core/
3	SDRAM controller core files are checked in	dinesha	5054d 17h	/sdr_ctrl/trunk/rtl/core/