OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] - Rev 69

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4025d 11h /sdr_ctrl/trunk/rtl/core/
64 CAS Latency support added for 4,5 dinesha 4343d 18h /sdr_ctrl/trunk/rtl/core/
55 FPGA Synthesis timing optimisation dinesha 4463d 10h /sdr_ctrl/trunk/rtl/core/
54 FPGA Timing Optimisation dinesha 4466d 08h /sdr_ctrl/trunk/rtl/core/
51 FPGA relating timing optimisation done dinesha 4467d 08h /sdr_ctrl/trunk/rtl/core/
50 Bug fix the request length is fixe dinesha 4469d 12h /sdr_ctrl/trunk/rtl/core/
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4470d 11h /sdr_ctrl/trunk/rtl/core/
46 test bench upgrade + rtl cleanup dinesha 4472d 12h /sdr_ctrl/trunk/rtl/core/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4472d 16h /sdr_ctrl/trunk/rtl/core/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4474d 14h /sdr_ctrl/trunk/rtl/core/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4476d 18h /sdr_ctrl/trunk/rtl/core/
36 Clean up dinesha 4477d 08h /sdr_ctrl/trunk/rtl/core/
33 clean up dinesha 4477d 11h /sdr_ctrl/trunk/rtl/core/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4479d 10h /sdr_ctrl/trunk/rtl/core/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4481d 13h /sdr_ctrl/trunk/rtl/core/
16 8 Bit SDRAM Support is added dinesha 4483d 09h /sdr_ctrl/trunk/rtl/core/
15 Port cleanup dinesha 4486d 09h /sdr_ctrl/trunk/rtl/core/
13 column bit are made progrmmable dinesha 4486d 10h /sdr_ctrl/trunk/rtl/core/
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4490d 10h /sdr_ctrl/trunk/rtl/core/
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4491d 08h /sdr_ctrl/trunk/rtl/core/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.