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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] - Rev 73


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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 1022d 23h /sdr_ctrl/trunk/rtl/core/
71 Warning cleanup dinesha 4068d 00h /sdr_ctrl/trunk/rtl/core/
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4068d 01h /sdr_ctrl/trunk/rtl/core/
64 CAS Latency support added for 4,5 dinesha 4386d 08h /sdr_ctrl/trunk/rtl/core/
55 FPGA Synthesis timing optimisation dinesha 4506d 00h /sdr_ctrl/trunk/rtl/core/
54 FPGA Timing Optimisation dinesha 4508d 22h /sdr_ctrl/trunk/rtl/core/
51 FPGA relating timing optimisation done dinesha 4509d 22h /sdr_ctrl/trunk/rtl/core/
50 Bug fix the request length is fixe dinesha 4512d 02h /sdr_ctrl/trunk/rtl/core/
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4513d 01h /sdr_ctrl/trunk/rtl/core/
46 test bench upgrade + rtl cleanup dinesha 4515d 02h /sdr_ctrl/trunk/rtl/core/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4515d 06h /sdr_ctrl/trunk/rtl/core/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4517d 04h /sdr_ctrl/trunk/rtl/core/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4519d 08h /sdr_ctrl/trunk/rtl/core/
36 Clean up dinesha 4519d 22h /sdr_ctrl/trunk/rtl/core/
33 clean up dinesha 4520d 01h /sdr_ctrl/trunk/rtl/core/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4522d 00h /sdr_ctrl/trunk/rtl/core/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4524d 04h /sdr_ctrl/trunk/rtl/core/
16 8 Bit SDRAM Support is added dinesha 4525d 23h /sdr_ctrl/trunk/rtl/core/
15 Port cleanup dinesha 4528d 23h /sdr_ctrl/trunk/rtl/core/
13 column bit are made progrmmable dinesha 4529d 00h /sdr_ctrl/trunk/rtl/core/

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