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URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] - Rev 73

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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 1020d 01h /sdr_ctrl/trunk/rtl/core/
71 Warning cleanup dinesha 4065d 02h /sdr_ctrl/trunk/rtl/core/
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4065d 03h /sdr_ctrl/trunk/rtl/core/
64 CAS Latency support added for 4,5 dinesha 4383d 10h /sdr_ctrl/trunk/rtl/core/
55 FPGA Synthesis timing optimisation dinesha 4503d 02h /sdr_ctrl/trunk/rtl/core/
54 FPGA Timing Optimisation dinesha 4506d 00h /sdr_ctrl/trunk/rtl/core/
51 FPGA relating timing optimisation done dinesha 4507d 01h /sdr_ctrl/trunk/rtl/core/
50 Bug fix the request length is fixe dinesha 4509d 04h /sdr_ctrl/trunk/rtl/core/
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4510d 04h /sdr_ctrl/trunk/rtl/core/
46 test bench upgrade + rtl cleanup dinesha 4512d 04h /sdr_ctrl/trunk/rtl/core/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4512d 09h /sdr_ctrl/trunk/rtl/core/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4514d 07h /sdr_ctrl/trunk/rtl/core/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4516d 10h /sdr_ctrl/trunk/rtl/core/
36 Clean up dinesha 4517d 01h /sdr_ctrl/trunk/rtl/core/
33 clean up dinesha 4517d 03h /sdr_ctrl/trunk/rtl/core/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4519d 02h /sdr_ctrl/trunk/rtl/core/
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4521d 06h /sdr_ctrl/trunk/rtl/core/
16 8 Bit SDRAM Support is added dinesha 4523d 01h /sdr_ctrl/trunk/rtl/core/
15 Port cleanup dinesha 4526d 02h /sdr_ctrl/trunk/rtl/core/
13 column bit are made progrmmable dinesha 4526d 02h /sdr_ctrl/trunk/rtl/core/
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4530d 03h /sdr_ctrl/trunk/rtl/core/
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4531d 00h /sdr_ctrl/trunk/rtl/core/
3 SDRAM controller core files are checked in dinesha 4537d 10h /sdr_ctrl/trunk/rtl/core/

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