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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_bank_ctl.v] - Rev 69

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Rev Log message Author Age Path
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4040d 02h /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
55 FPGA Synthesis timing optimisation dinesha 4478d 00h /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
54 FPGA Timing Optimisation dinesha 4480d 22h /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
51 FPGA relating timing optimisation done dinesha 4481d 23h /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
50 Bug fix the request length is fixe dinesha 4484d 03h /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4491d 08h /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
15 Port cleanup dinesha 4501d 00h /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4505d 22h /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
3 SDRAM controller core files are checked in dinesha 4512d 09h /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v

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