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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_bank_ctl.v] - Rev 45


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Rev Log message Author Age Path
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4557d 15h /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
15 Port cleanup dinesha 4567d 07h /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4572d 05h /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
3 SDRAM controller core files are checked in dinesha 4578d 15h /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v

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