URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_bank_ctl.v] - Rev 67

Rev	Log message	Author	Age	Path
55	FPGA Synthesis timing optimisation	dinesha	4475d 07h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
54	FPGA Timing Optimisation	dinesha	4478d 04h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
51	FPGA relating timing optimisation done	dinesha	4479d 05h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
50	Bug fix the request length is fixe	dinesha	4481d 09h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4488d 14h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
15	Port cleanup	dinesha	4498d 06h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4503d 04h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v
3	SDRAM controller core files are checked in	dinesha	4509d 15h	/sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v