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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_bank_fsm.v] - Rev 69

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Rev Log message Author Age Path
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4014d 08h /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v
55 FPGA Synthesis timing optimisation dinesha 4452d 07h /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v
54 FPGA Timing Optimisation dinesha 4455d 05h /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v
51 FPGA relating timing optimisation done dinesha 4456d 05h /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v
50 Bug fix the request length is fixe dinesha 4458d 09h /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4465d 15h /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4480d 05h /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v

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