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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_bs_convert.v] - Rev 50

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Rev Log message Author Age Path
50 Bug fix the request length is fixe dinesha 4451d 17h /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4452d 16h /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4454d 21h /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4456d 19h /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4458d 22h /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4461d 14h /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v
16 8 Bit SDRAM Support is added dinesha 4465d 13h /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4473d 12h /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v
3 SDRAM controller core files are checked in dinesha 4479d 23h /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v

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