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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_core.v] - Rev 69


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Rev Log message Author Age Path
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 3960d 17h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
55 FPGA Synthesis timing optimisation dinesha 4398d 16h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
54 FPGA Timing Optimisation dinesha 4401d 13h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
51 FPGA relating timing optimisation done dinesha 4402d 14h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
50 Bug fix the request length is fixe dinesha 4404d 18h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4405d 17h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
46 test bench upgrade + rtl cleanup dinesha 4407d 18h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4407d 22h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4409d 20h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4411d 23h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
33 clean up dinesha 4412d 16h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4414d 15h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4416d 19h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
16 8 Bit SDRAM Support is added dinesha 4418d 14h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
15 Port cleanup dinesha 4421d 15h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
13 column bit are made progrmmable dinesha 4421d 15h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4425d 16h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4426d 13h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
3 SDRAM controller core files are checked in dinesha 4433d 00h /sdr_ctrl/trunk/rtl/core/sdrc_core.v

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