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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_core.v] - Rev 44

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Rev Log message Author Age Path
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 3960d 01h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 3962d 04h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
33 clean up dinesha 3962d 21h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 3964d 20h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 3967d 00h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
16 8 Bit SDRAM Support is added dinesha 3968d 19h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
15 Port cleanup dinesha 3971d 20h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
13 column bit are made progrmmable dinesha 3971d 20h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
9 SDR Bus width parameter passing issue across the models are fixed dinesha 3975d 21h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 3976d 18h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
3 SDRAM controller core files are checked in dinesha 3983d 05h /sdr_ctrl/trunk/rtl/core/sdrc_core.v

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