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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_core.v] - Rev 44

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Rev Log message Author Age Path
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4514d 09h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4516d 12h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
33 clean up dinesha 4517d 05h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4519d 04h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4521d 08h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
16 8 Bit SDRAM Support is added dinesha 4523d 03h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
15 Port cleanup dinesha 4526d 04h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
13 column bit are made progrmmable dinesha 4526d 04h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4530d 05h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4531d 02h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
3 SDRAM controller core files are checked in dinesha 4537d 13h /sdr_ctrl/trunk/rtl/core/sdrc_core.v

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