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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_core.v] - Rev 50

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Rev Log message Author Age Path
50 Bug fix the request length is fixe dinesha 4540d 11h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4541d 10h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
46 test bench upgrade + rtl cleanup dinesha 4543d 11h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4543d 15h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4545d 13h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4547d 17h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
33 clean up dinesha 4548d 09h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4550d 08h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4552d 12h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
16 8 Bit SDRAM Support is added dinesha 4554d 07h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
15 Port cleanup dinesha 4557d 08h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
13 column bit are made progrmmable dinesha 4557d 08h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4561d 09h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4562d 06h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
3 SDRAM controller core files are checked in dinesha 4568d 17h /sdr_ctrl/trunk/rtl/core/sdrc_core.v

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