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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_core.v] - Rev 69

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Rev Log message Author Age Path
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4004d 13h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
55 FPGA Synthesis timing optimisation dinesha 4442d 11h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
54 FPGA Timing Optimisation dinesha 4445d 09h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
51 FPGA relating timing optimisation done dinesha 4446d 10h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
50 Bug fix the request length is fixe dinesha 4448d 14h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4449d 13h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
46 test bench upgrade + rtl cleanup dinesha 4451d 13h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4451d 18h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4453d 16h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4455d 19h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
33 clean up dinesha 4456d 12h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4458d 11h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4460d 15h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
16 8 Bit SDRAM Support is added dinesha 4462d 10h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
15 Port cleanup dinesha 4465d 11h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
13 column bit are made progrmmable dinesha 4465d 11h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4469d 12h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4470d 09h /sdr_ctrl/trunk/rtl/core/sdrc_core.v
3 SDRAM controller core files are checked in dinesha 4476d 19h /sdr_ctrl/trunk/rtl/core/sdrc_core.v

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