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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_define.v] - Rev 73


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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 836d 05h /sdr_ctrl/trunk/rtl/core/sdrc_define.v
54 FPGA Timing Optimisation dinesha 4322d 04h /sdr_ctrl/trunk/rtl/core/sdrc_define.v
51 FPGA relating timing optimisation done dinesha 4323d 05h /sdr_ctrl/trunk/rtl/core/sdrc_define.v
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4332d 14h /sdr_ctrl/trunk/rtl/core/sdrc_define.v
15 Port cleanup dinesha 4342d 05h /sdr_ctrl/trunk/rtl/core/sdrc.def
13 column bit are made progrmmable dinesha 4342d 06h /sdr_ctrl/trunk/rtl/core/sdrc.def
3 SDRAM controller core files are checked in dinesha 4353d 14h /sdr_ctrl/trunk/rtl/core/sdrc.def

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