URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_req_gen.v] - Rev 73

Rev	Log message	Author	Age	Path
73	sdram bug in FPGA mode + 8/16 bit address map fix	dinesha	970d 03h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
69	SDRAM address bit increased from 12 bit to 13 bit	dinesha	4015d 05h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
55	FPGA Synthesis timing optimisation	dinesha	4453d 04h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
54	FPGA Timing Optimisation	dinesha	4456d 02h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
51	FPGA relating timing optimisation done	dinesha	4457d 03h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
50	Bug fix the request length is fixe	dinesha	4459d 06h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4460d 06h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
46	test bench upgrade + rtl cleanup	dinesha	4462d 06h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4462d 11h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4466d 12h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
33	clean up	dinesha	4467d 05h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
16	8 Bit SDRAM Support is added	dinesha	4473d 03h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
15	Port cleanup	dinesha	4476d 04h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
13	column bit are made progrmmable	dinesha	4476d 04h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
3	SDRAM controller core files are checked in	dinesha	4487d 12h	/sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v