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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_req_gen.v] - Rev 73


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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 353d 08h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 3398d 10h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
55 FPGA Synthesis timing optimisation dinesha 3836d 08h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
54 FPGA Timing Optimisation dinesha 3839d 06h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
51 FPGA relating timing optimisation done dinesha 3840d 07h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
50 Bug fix the request length is fixe dinesha 3842d 11h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 3843d 10h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
46 test bench upgrade + rtl cleanup dinesha 3845d 10h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 3845d 15h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 3849d 16h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
33 clean up dinesha 3850d 09h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
16 8 Bit SDRAM Support is added dinesha 3856d 07h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
15 Port cleanup dinesha 3859d 08h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
13 column bit are made progrmmable dinesha 3859d 08h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v
3 SDRAM controller core files are checked in dinesha 3870d 16h /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v

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