URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_xfr_ctl.v] - Rev 54

Rev	Log message	Author	Age	Path
54	FPGA Timing Optimisation	dinesha	5201d 00h	/sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
51	FPGA relating timing optimisation done	dinesha	5202d 00h	/sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
50	Bug fix the request length is fixe	dinesha	5204d 04h	/sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	5207d 08h	/sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	5211d 10h	/sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
36	Clean up	dinesha	5212d 00h	/sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
3	SDRAM controller core files are checked in	dinesha	5232d 10h	/sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v