URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_xfr_ctl.v] - Rev 69

Rev	Log message	Author	Age	Path
69	SDRAM address bit increased from 12 bit to 13 bit	dinesha	4022d 01h	/sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
64	CAS Latency support added for 4,5	dinesha	4340d 08h	/sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
55	FPGA Synthesis timing optimisation	dinesha	4460d 00h	/sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
54	FPGA Timing Optimisation	dinesha	4462d 22h	/sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
51	FPGA relating timing optimisation done	dinesha	4463d 22h	/sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
50	Bug fix the request length is fixe	dinesha	4466d 02h	/sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4469d 06h	/sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4473d 08h	/sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
36	Clean up	dinesha	4473d 22h	/sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
3	SDRAM controller core files are checked in	dinesha	4494d 08h	/sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v