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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_xfr_ctl.v] - Rev 71

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Rev Log message Author Age Path
71 Warning cleanup dinesha 4241d 13h /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4241d 14h /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
64 CAS Latency support added for 4,5 dinesha 4559d 21h /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
55 FPGA Synthesis timing optimisation dinesha 4679d 13h /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
54 FPGA Timing Optimisation dinesha 4682d 10h /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
51 FPGA relating timing optimisation done dinesha 4683d 11h /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
50 Bug fix the request length is fixe dinesha 4685d 15h /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4688d 19h /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4692d 20h /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
36 Clean up dinesha 4693d 11h /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v
3 SDRAM controller core files are checked in dinesha 4713d 21h /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v

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