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[/] [sdr_ctrl/] [trunk/] [rtl/] [top/] - Rev 71


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Rev Log message Author Age Path
71 Warning cleanup dinesha 4044d 04h /sdr_ctrl/trunk/rtl/top/
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4044d 06h /sdr_ctrl/trunk/rtl/top/
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4362d 05h /sdr_ctrl/trunk/rtl/top/
60 warning cleanup dinesha 4481d 12h /sdr_ctrl/trunk/rtl/top/
55 FPGA Synthesis timing optimisation dinesha 4482d 04h /sdr_ctrl/trunk/rtl/top/
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4489d 06h /sdr_ctrl/trunk/rtl/top/
46 test bench upgrade + rtl cleanup dinesha 4491d 06h /sdr_ctrl/trunk/rtl/top/
38 Port Name clean up dinesha 4495d 10h /sdr_ctrl/trunk/rtl/top/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4495d 12h /sdr_ctrl/trunk/rtl/top/
33 clean up dinesha 4496d 05h /sdr_ctrl/trunk/rtl/top/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4498d 04h /sdr_ctrl/trunk/rtl/top/

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