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[/] [sdr_ctrl/] [trunk/] [rtl/] [top/] - Rev 58

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Rev Log message Author Age Path
55 FPGA Synthesis timing optimisation dinesha 4628d 12h /sdr_ctrl/trunk/rtl/top/
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4635d 13h /sdr_ctrl/trunk/rtl/top/
46 test bench upgrade + rtl cleanup dinesha 4637d 14h /sdr_ctrl/trunk/rtl/top/
38 Port Name clean up dinesha 4641d 18h /sdr_ctrl/trunk/rtl/top/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4641d 19h /sdr_ctrl/trunk/rtl/top/
33 clean up dinesha 4642d 12h /sdr_ctrl/trunk/rtl/top/
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4644d 11h /sdr_ctrl/trunk/rtl/top/

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