URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [top/] - Rev 70

Rev	Log message	Author	Age	Path
69	SDRAM address bit increased from 12 bit to 13 bit	dinesha	4027d 13h	/sdr_ctrl/trunk/rtl/top/
66	dwm tw, bl paramter are passed on the wb2sdrc module	dinesha	4345d 13h	/sdr_ctrl/trunk/rtl/top/
60	warning cleanup	dinesha	4464d 20h	/sdr_ctrl/trunk/rtl/top/
55	FPGA Synthesis timing optimisation	dinesha	4465d 12h	/sdr_ctrl/trunk/rtl/top/
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4472d 14h	/sdr_ctrl/trunk/rtl/top/
46	test bench upgrade + rtl cleanup	dinesha	4474d 14h	/sdr_ctrl/trunk/rtl/top/
38	Port Name clean up	dinesha	4478d 18h	/sdr_ctrl/trunk/rtl/top/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4478d 20h	/sdr_ctrl/trunk/rtl/top/
33	clean up	dinesha	4479d 13h	/sdr_ctrl/trunk/rtl/top/
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4481d 12h	/sdr_ctrl/trunk/rtl/top/