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[/] [sdr_ctrl/] [trunk/] [rtl/] [top/] [sdrc_top.v] - Rev 71

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Rev Log message Author Age Path
71 Warning cleanup dinesha 3956d 04h /sdr_ctrl/trunk/rtl/top/sdrc_top.v
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 3956d 05h /sdr_ctrl/trunk/rtl/top/sdrc_top.v
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4274d 04h /sdr_ctrl/trunk/rtl/top/sdrc_top.v
60 warning cleanup dinesha 4393d 12h /sdr_ctrl/trunk/rtl/top/sdrc_top.v
55 FPGA Synthesis timing optimisation dinesha 4394d 04h /sdr_ctrl/trunk/rtl/top/sdrc_top.v
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4401d 05h /sdr_ctrl/trunk/rtl/top/sdrc_top.v
46 test bench upgrade + rtl cleanup dinesha 4403d 06h /sdr_ctrl/trunk/rtl/top/sdrc_top.v
38 Port Name clean up dinesha 4407d 10h /sdr_ctrl/trunk/rtl/top/sdrc_top.v
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4407d 12h /sdr_ctrl/trunk/rtl/top/sdrc_top.v
33 clean up dinesha 4408d 05h /sdr_ctrl/trunk/rtl/top/sdrc_top.v
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4410d 04h /sdr_ctrl/trunk/rtl/top/sdrc_top.v

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