URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [top/] [sdrc_top.v] - Rev 69

Rev	Log message	Author	Age	Path
69	SDRAM address bit increased from 12 bit to 13 bit	dinesha	4022d 05h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
66	dwm tw, bl paramter are passed on the wb2sdrc module	dinesha	4340d 04h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
60	warning cleanup	dinesha	4459d 12h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
55	FPGA Synthesis timing optimisation	dinesha	4460d 04h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4467d 05h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
46	test bench upgrade + rtl cleanup	dinesha	4469d 06h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
38	Port Name clean up	dinesha	4473d 10h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4473d 12h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
33	clean up	dinesha	4474d 05h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4476d 04h	/sdr_ctrl/trunk/rtl/top/sdrc_top.v