URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [top] - Rev 71

Rev	Log message	Author	Age	Path
71	Warning cleanup	dinesha	4029d 17h	/sdr_ctrl/trunk/rtl/top
69	SDRAM address bit increased from 12 bit to 13 bit	dinesha	4029d 18h	/sdr_ctrl/trunk/rtl/top
66	dwm tw, bl paramter are passed on the wb2sdrc module	dinesha	4347d 18h	/sdr_ctrl/trunk/rtl/top
60	warning cleanup	dinesha	4467d 01h	/sdr_ctrl/trunk/rtl/top
55	FPGA Synthesis timing optimisation	dinesha	4467d 17h	/sdr_ctrl/trunk/rtl/top
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4474d 19h	/sdr_ctrl/trunk/rtl/top
46	test bench upgrade + rtl cleanup	dinesha	4476d 19h	/sdr_ctrl/trunk/rtl/top
38	Port Name clean up	dinesha	4480d 23h	/sdr_ctrl/trunk/rtl/top
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4481d 01h	/sdr_ctrl/trunk/rtl/top
33	clean up	dinesha	4481d 18h	/sdr_ctrl/trunk/rtl/top
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4483d 17h	/sdr_ctrl/trunk/rtl/top