URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [wb2sdrc/] - Rev 65

Rev	Log message	Author	Age	Path
59	Control path request and data are register now for better FPGA timing	dinesha	5054d 11h	/sdr_ctrl/trunk/rtl/wb2sdrc/
55	FPGA Synthesis timing optimisation	dinesha	5055d 03h	/sdr_ctrl/trunk/rtl/wb2sdrc/
42	Bug fix in read access is fixed	dinesha	5066d 09h	/sdr_ctrl/trunk/rtl/wb2sdrc/
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	5067d 04h	/sdr_ctrl/trunk/rtl/wb2sdrc/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	5068d 11h	/sdr_ctrl/trunk/rtl/wb2sdrc/
33	clean up	dinesha	5069d 04h	/sdr_ctrl/trunk/rtl/wb2sdrc/
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	5071d 03h	/sdr_ctrl/trunk/rtl/wb2sdrc/