Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [wb2sdrc/] [wb2sdrc.v] - Rev 69


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Rev Log message Author Age Path
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 3868d 02h /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v
59 Control path request and data are register now for better FPGA timing dinesha 4305d 09h /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v
55 FPGA Synthesis timing optimisation dinesha 4306d 01h /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v
42 Bug fix in read access is fixed dinesha 4317d 07h /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4318d 02h /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4319d 09h /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v
33 clean up dinesha 4320d 02h /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4322d 01h /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v

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