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[/] [sdr_ctrl/] [trunk/] [rtl/] [wb2sdrc/] [wb2sdrc.v] - Rev 40

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Rev Log message Author Age Path
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4527d 15h /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4528d 22h /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v
33 clean up dinesha 4529d 15h /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4531d 14h /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v

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