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[/] [sdr_ctrl/] [trunk/] [rtl/] [wb2sdrc] - Rev 69


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Rev Log message Author Age Path
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 3957d 01h /sdr_ctrl/trunk/rtl/wb2sdrc
59 Control path request and data are register now for better FPGA timing dinesha 4394d 08h /sdr_ctrl/trunk/rtl/wb2sdrc
55 FPGA Synthesis timing optimisation dinesha 4394d 23h /sdr_ctrl/trunk/rtl/wb2sdrc
42 Bug fix in read access is fixed dinesha 4406d 06h /sdr_ctrl/trunk/rtl/wb2sdrc
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4407d 00h /sdr_ctrl/trunk/rtl/wb2sdrc
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4408d 07h /sdr_ctrl/trunk/rtl/wb2sdrc
33 clean up dinesha 4409d 00h /sdr_ctrl/trunk/rtl/wb2sdrc
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4410d 23h /sdr_ctrl/trunk/rtl/wb2sdrc

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