URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl] - Rev 73

Rev	Log message	Author	Age	Path
38	Port Name clean up	dinesha	4490d 11h	/sdr_ctrl/trunk/rtl
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4490d 13h	/sdr_ctrl/trunk/rtl
36	Clean up	dinesha	4491d 03h	/sdr_ctrl/trunk/rtl
33	clean up	dinesha	4491d 06h	/sdr_ctrl/trunk/rtl
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4493d 05h	/sdr_ctrl/trunk/rtl
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4495d 09h	/sdr_ctrl/trunk/rtl
16	8 Bit SDRAM Support is added	dinesha	4497d 04h	/sdr_ctrl/trunk/rtl
15	Port cleanup	dinesha	4500d 04h	/sdr_ctrl/trunk/rtl
13	column bit are made progrmmable	dinesha	4500d 05h	/sdr_ctrl/trunk/rtl
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4504d 05h	/sdr_ctrl/trunk/rtl