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[/] [sdr_ctrl/] [trunk/] [verif/] - Rev 73


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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 577d 00h /sdr_ctrl/trunk/verif/
72 Command Clean up for model-sim mode dinesha 3570d 09h /sdr_ctrl/trunk/verif/
70 Warning Cleanup dinesha 3622d 01h /sdr_ctrl/trunk/verif/
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 3622d 02h /sdr_ctrl/trunk/verif/
65 Updated Log file with CAS latency support 4,5 dinesha 3940d 09h /sdr_ctrl/trunk/verif/
56 FPGA Synth optimisation dinesha 4060d 01h /sdr_ctrl/trunk/verif/
53 Test bench upgradation dinesha 4063d 23h /sdr_ctrl/trunk/verif/
49 clean up dinesha 4067d 02h /sdr_ctrl/trunk/verif/
48 top-level cleanup dinesha 4067d 02h /sdr_ctrl/trunk/verif/
46 test bench upgrade + rtl cleanup dinesha 4069d 03h /sdr_ctrl/trunk/verif/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4069d 08h /sdr_ctrl/trunk/verif/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4071d 06h /sdr_ctrl/trunk/verif/
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4071d 07h /sdr_ctrl/trunk/verif/
39 Test Bench upgradation with bigger data burst size dinesha 4072d 02h /sdr_ctrl/trunk/verif/
38 Port Name clean up dinesha 4073d 07h /sdr_ctrl/trunk/verif/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4073d 09h /sdr_ctrl/trunk/verif/
33 clean up dinesha 4074d 02h /sdr_ctrl/trunk/verif/
32 Debug is enable through +define dinesha 4076d 01h /sdr_ctrl/trunk/verif/
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4076d 01h /sdr_ctrl/trunk/verif/
29 SDRAM top and core related run file list are added into svn dinesha 4076d 01h /sdr_ctrl/trunk/verif/

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