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[/] [sdr_ctrl/] [trunk/] [verif/] - Rev 27

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Rev Log message Author Age Path
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4526d 12h /sdr_ctrl/trunk/verif/
26 invalid log files are removed dinesha 4526d 12h /sdr_ctrl/trunk/verif/
25 tb.sv is renamed as tb_top dinesha 4526d 13h /sdr_ctrl/trunk/verif/
24 Clean Up dinesha 4526d 13h /sdr_ctrl/trunk/verif/
22 Pad sdram clock added dinesha 4527d 18h /sdr_ctrl/trunk/verif/
21 Clean up dinesha 4527d 18h /sdr_ctrl/trunk/verif/
20 8 Bit SDARM support is added dinesha 4529d 13h /sdr_ctrl/trunk/verif/
19 8 Bit SDRAM Support added dinesha 4529d 13h /sdr_ctrl/trunk/verif/
18 8 Bit SDRAM Support is added dinesha 4529d 13h /sdr_ctrl/trunk/verif/
17 micron 8 bit memory models are added into svn dinesha 4529d 13h /sdr_ctrl/trunk/verif/
14 Unnecessary device config are removed dinesha 4532d 14h /sdr_ctrl/trunk/verif/
12 Column Bits are made programmable dinesha 4532d 14h /sdr_ctrl/trunk/verif/
10 Waveform files are added into SVN dinesha 4535d 15h /sdr_ctrl/trunk/verif/
8 test bench files are added into SVN dinesha 4536d 15h /sdr_ctrl/trunk/verif/
7 SDRAM Memory Models are added into SVN dinesha 4536d 15h /sdr_ctrl/trunk/verif/
6 Golden Log files are added into SVN dinesha 4536d 15h /sdr_ctrl/trunk/verif/
5 Run files are updated into SVN dinesha 4536d 15h /sdr_ctrl/trunk/verif/
2 dinesha 4546d 14h /sdr_ctrl/trunk/verif/

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